How to use Claude to simulate relay Tetris in Verilog
Claude designed Tetris using 1,400 relays, compiled the netlist to Verilog and compared the simulated port against its original simulator. The author reports matching behavior and a visualization, with physical boards still pending.
news.ycombinator.com
Suggested prompt
Suggested prompt written by Agents In Use, not the source author. Replace bracketed inputs and review tool permissions first.
Design [game or circuit] in [relay simulator], then compile its netlist to Verilog for [chip target]. Run both simulations and compare corresponding relay states. Report mismatches and create a visualization of one run, clearly distinguishing simulation results from physical testing.
Reach people exploring AI agents
See placements →Evidence at a glance
Sourced account- Source poster / publisher
- gregsadetsky
- Original account
- Read the source ↗
- Published
- Source link checked
- Reported result
- The author reports a working 1,400-relay Tetris design whose Verilog simulation matched the original relay simulator, plus a visualization of a simulated run. Physical-board operation was not reported.
- Human involvement
- The author requested the design and visualization and reported matching simulation results; the post describes no physical-hardware test.
A linked account supports attribution. It does not mean we independently reproduced its result.
Report an issue with this case
Open correction emailOpens your email app with the case link included. Nothing is sent automatically.
How the agent did it
- Have Claude design working Tetris using 1,400 simulated relays.
- Compile the relay netlist into Verilog.
- Run the Verilog port on the simulated chip.
While waiting for two iCEBreaker boards to arrive, the author used Claude, called Fable in the post, for hardware experiments entirely in simulation. One experiment began with a Minivac web simulator that the author and Fable had built.
The author asked Claude to design working Tetris using 1,400 relays for that simulator. Claude then compiled the relay netlist to Verilog and ran it on a simulated chip. It compared the port against the original simulator relay by relay, with the author reporting that everything matched. The reported total LLM time was less than an hour.
The author also had Claude create a visualization showing the netlist blinking through a simulated run. This supplied another output beyond the game and Verilog port. The account does not claim that Tetris had been tested on physical hardware; the boards were still in the mail.
A separate experiment ported TinyStories to the same chip target and reduced it to fit the chip size. That result, too, was reported in simulation.
Who it's for: Hardware enthusiasts exploring agent-assisted digital design who want simulation comparisons before attempting a physical-board implementation.
Prompt
Suggested prompt (written by Agents In Use, not the author's)
Source: Hacker News · gregsadetsky
Frequently asked questions
How was the Verilog port checked?
Claude ran the port on the simulated chip and compared it relay by relay against the original simulator. The author reports that all comparisons matched.
Was the Tetris design running on physical hardware?
The reported work was entirely in simulation. The author said two iCEBreaker boards were still in the mail.
What additional output did Claude create?
The author asked Claude to create a visualization of the relay netlist blinking through one simulated run.
More details
Remaining steps
- Compare the port relay by relay against the original simulator.
- Create a visualization of the netlist during a simulated run.
About this account
Claude designed the relay game, translated the netlist, ran the simulation comparison and generated a visualization at the author's direction.
Platform: Hacker News. Attribution: https://news.ycombinator.com/item?id=49531778. Prompt: Suggested (written by Agents In Use, not the author's). Sourced by the Agents In Use pipeline.
Credit: gregsadetsky on Hacker News
Source published
Added to Agents In Use
Source checked
Tools and topics
Claude · Minivac web simulator · Verilog · Chip simulation
FPGA · Verilog · Simulation · Tetris · Relay logic
Editorial completeness: 100/100. Measures documented fields, not agent performance or verified outcomes.