How to use Claude to correct a mirrored PCB export
Claude traced clustered PCB routing failures to mirrored capacitor exports, fixed geometry parity and the clean verdict, with two connections still open.
punkfab.com
Original prompt
Shared by the source author. See source notes for context.
try this again side by side with the original
Reach people exploring AI agents
See placements →What happened
The export defect and misleading clean verdict were corrected, but two open connections still required local finishing before fabrication.
Reported by Dan Newcome — PUNKFAB logHow the agent did it
- Claude reran the existing board pipeline and examined the short and open-net markers.
- It compared native and exported pad positions, then corrected the three capacitors’ side-specific DSN definitions.
- The reroute removed the short, and the check was changed to fail when two remaining nets were still open.
Where a person stepped in
Newcome requested a side-by-side rerun and examined the resulting board markers; unresolved routing stayed visible instead of being accepted as fabrication readiness.
Dan Newcome asked Claude to rerun the routing pipeline for einhander, a one-handed USB MIDI board. The initial result had a short and six open connections. Rather than treating each marker as an independent routing problem, the agent traced a shared export defect.
Three top-side capacitors inherited a bottom-side footprint image in the DSN export. KiCad displayed their positions correctly, while the exported pad geometry was mirrored. Claude added a side-splitting script that compared KiCad’s board-coordinate pad positions with the DSN image and gave the affected capacitors their own corrected definitions. A rotated RP2040 footprint was a false lead, which made coordinate conventions important.
Rerouting removed the short, but two connections remained open. The project’s own verdict had printed a clean result despite those opens, so that gate was corrected to fail. Further router attempts did not complete the missing QSPI clock and USB data connections.
The result was a reusable export repair and a more honest check, with local finishing still required. It did not produce a fabrication-ready board. The owner initiated the rerun and inspected the reported connection failures.
Prompt
Original prompt
Source: PUNKFAB log · Dan Newcome
Frequently asked questions
What caused the clustered defects?
Top-side capacitors inherited a mirrored bottom-side export image.
Did the router finish the board?
No. Two connections remained open after the short disappeared.
What changed in the completion gate?
Open connections now prevent a clean verdict.
More details
About this account
Claude reran the existing board pipeline and examined the short and open-net markers. It compared native and exported pad positions, then corrected the three capacitors’ side-specific DSN definitions.
Opened original dated rerouting log. The shared prompt excerpt is exact. This account covers export parity and routing gates; the separate ArtNode power-path revision is a different board and task. Original prompt excerpt.
Credit: Dan Newcome — PUNKFAB log
Source published 1 Oct 2026
Source checked 14 Oct 2026
Tools and topics
Claude Code · KiCad · tscircuit · Freerouting · Python
PCB export · coordinate transforms · routing checks
Editorial completeness: 100/100. Measures documented fields, not agent performance or verified outcomes.