How to use Claude to route a CH32 tester PCB
Claude Code laid out a CH32 tester with EasyEDA and Freerouting. Net readbacks caught missing grounds; manufacturing and physical checks remained unfinished.
jlcpcb.com
Suggested prompt
Suggested prompt written by Agents In Use, not the source author. Replace bracketed inputs and review tool permissions first.
Lay out this CH32 tester from the supplied connection document and pin map. Read back actual footprint pins and nets, check missing grounds and overlaps, route through the supported DSN workflow and verify imported connectivity and DRC. Stop before manufacturing until I inspect exports and mechanical details.
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See placements →What happened
The reported tester PCB reached clean final DRC through readbacks and external routing. Manufacturing exports, physical operation and thermal and mechanical checks remained unverified.
Reported by JLCPCB — Engineering blogHow the agent did it
- The operator supplied the tester specification, connection document and MCU pin map.
- Claude selected real footprints and read back pins and nets to catch missing ground connections.
- The agent placed parts, routed through Freerouting and checked imported connectivity and DRC.
Where a person stepped in
The operator supplied pin maps and specifications, approved editor dialogs, checked sourcing and retained manufacturing, thermal and mechanical reviews.
JLCPCB documented using Claude Code to lay out a CH32V006 tester in EasyEDA through a local API bridge. The operator supplied a multi-page specification, a connection document and the microcontroller pin map before the agent began placing actual sourced parts.
Claude read back footprint pins and connectivity instead of relying only on editor screenshots. That check caught missing ground connections. It also exposed a tool behavior that could reset part attributes when a modification changed only the name, requiring the agent to restore the complete attribute set.
The placement process used explicit zones and scripted checks for overlaps and clearance. EasyEDA's API did not provide an autorouter, so Claude exported a DSN file, ran Freerouting and imported vias before tracks. The final workflow checked open connections and design-rule results rather than treating a successful import as completion.
The reported artifact had a clean final DRC, but remained a design rather than a proven tester. Stock substitutions, modal approvals and some editor logs still required the operator. Manufacturing exports had not yet been inspected, and thermal, polarity and mechanical details remained manual checks. The source therefore supports a concrete automated layout workflow with unresolved release checkpoints.
Prompt
Suggested prompt (written by Agents In Use, not the author's)
Source: Engineering blog · JLCPCB
Frequently asked questions
Why did the agent read back nets?
It caught missing ground connections that the initial design had not included.
How was routing performed?
Claude exported DSN, ran Freerouting and imported vias before tracks.
Was the board physically validated?
No. Manufacturing exports and physical, thermal and mechanical checks remained outstanding.
More details
About this account
The operator supplied the tester specification, connection document and MCU pin map. Claude selected real footprints and read back pins and nets to catch missing ground connections.
Firsthand publisher case study opened. Final DRC passed, but Gerbers, BOM and placement exports had not been inspected and the board was not physically validated. Suggested prompt written by Agents In Use; no original task prompt was published in the verified account.
Credit: JLCPCB — Engineering blog
Source published 13 Oct 2026
Source checked 14 Oct 2026
Tools and topics
Claude Code · EasyEDA · Freerouting · LCSC
PCB layout · Connectivity checks
Editorial completeness: 100/100. Measures documented fields, not agent performance or verified outcomes.